The present invention relates to an input buffer, and more particularly, to an input buffer for a semiconductor memory device.
In a conventional input buffer, the threshold value thereof is crucial. Here, high or low logical threshold level is adjusted by regulating the dimensions of a PMOS transistor and NMOS transistor which constitute an inverter. In general, since about 1.5 V (the middle value of typical voltage levels of 0 V and 3 V) is set as the logical threshold level, if an input signal has a transition time of 3 ns, a basic delay of 1.5 ns occurs. Also, the driving capability of the NMOS transistor and PMOS transistor are made to be the same by setting a middle value of the high or low logical threshold level. As a result, the path of direct current is formed about 1.5 V of the input signal and the speed slows down.
FIG. 1 is a circuit diagram of a conventional input buffer.
In FIG. 1, an input signal D is applied for two buffering inverters 1 and 2 to be cascade-connected and a buffered input signal DI is then output.
FIG. 2 shows a result of simulation of the circuit shown in FIG. 1.
In FIG. 2, when an input signal D rises from a low level to a high level, there is a delay of about 0.95 ns. When the input signal D falls from a high level to a low level, there is a delay of about 1.1 ns.
Therefore, in a conventional input buffer, since the logical threshold levels for logic "high" and logic "low" inputs are adjusted by the threshold levels of PMOS transistor and NMOS transistor constituting the inverter, disadvantages are resulted in that speed is decreased and direct current may flow during operation.